We estimate Google is the largest single owner of AI compute, holding about one quarter of global cumulative capacity as of Q4 2025. Notably among hyperscalers, Google’s compute comes primarily from its own custom TPU chips rather than NVIDIA’s GPUs.
| Name | Chip manufacturer | Owner | Start date | End date | Compute estimate in H100e (median) | H100e (5th percentile) | H100e (95th percentile) | Number of Units (median) | Number of Units (5th percentile) | Number of Units (95th percentile) | Power in MW (median) | Power in MW (5th percentile) | Power in MW (95th percentile) | Source / Link | Notes | Last Modified By | Last Modified | Incomplete |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Amazon cumulative Trainium through Q4 2025 | Amazon | Amazon | 1/1/2024 | 12/31/2025 | 1,020,727 | 907,525 | 1,164,343 | 1,856,963 | 1,559,233 | 2,421,792 | 840 | 730 | 1,016 | Estimates generated on: 03-10-2026 10:46 | ||||
| Amazon cumulative Nvidia through Q4 2025 | Nvidia | Amazon | 1/1/2022 | 12/31/2025 | 1,439,676 | 1,114,045 | 1,854,069 | 918,763 | 706,991 | 1,190,396 | 839 | 649 | 1,080 | Estimates generated on: 03-31-2026 17:30 | ||||
| Google cumulative Nvidia through Q4 2025 | Nvidia | 1/1/2022 | 12/31/2025 | 1,224,942 | 946,384 | 1,575,144 | 819,162 | 626,537 | 1,061,299 | 724 | 558 | 931 | Estimates generated on: 03-31-2026 17:30 | |||||
| Google cumulative TPU through Q4 2025 | 1/1/2023 | 12/31/2025 | 3,812,878 | 3,083,116 | 4,537,332 | 6,136,449 | 4,918,260 | 7,435,206 | 2,223 | 1,813 | 2,653 | Estimates generated on: 03-27-2026 18:13 | ||||||
| Meta cumulative AMD through Q4 2025 | AMD | Meta | 10/1/2025 | 12/31/2025 | 581,384 | 475,387 | 691,594 | 386,033 | 317,060 | 457,330 | 329 | 269 | 391 | Estimates generated on: 03-30-2026 | ||||
| Meta cumulative Nvidia through Q4 2025 | Nvidia | Meta | 1/1/2022 | 12/31/2025 | 1,842,317 | 1,426,111 | 2,383,663 | 1,195,289 | 914,903 | 1,550,154 | 1,079 | 834 | 1,395 | Estimates generated on: 03-31-2026 17:30 | ||||
| Microsoft cumulative AMD through Q4 2025 | AMD | Microsoft | 10/1/2025 | 12/31/2025 | 328,923 | 238,861 | 439,433 | 218,529 | 159,419 | 291,830 | 186 | 135 | 249 | Estimates generated on: 03-30-2026 | ||||
| Microsoft cumulative Nvidia through Q4 2025 | Nvidia | Microsoft | 1/1/2022 | 12/31/2025 | 3,175,534 | 2,443,591 | 4,105,459 | 2,119,743 | 1,625,042 | 2,775,971 | 1,879 | 1,448 | 2,442 | Estimates generated on: 03-31-2026 17:30 |
Note that Microsoft and Meta also have in-house-designed chips that we do not currently track, though we believe these have a negligible impact on our estimates.
Epoch's work is free to use, distribute, and reproduce provided the source and authors are credited under the Creative Commons BY license.
Learn more about this graph
Using estimates from the AI Chip Owners hub, we show the cumulative amount of AI compute held by each of the world’s four largest compute owners: Google, Microsoft, Meta, and Amazon, as of Q4 2025. We break out compute by chip manufacturer and find that Google held the most compute as of Q4 2025, driven by its in-house-designed TPU chips.
Data
The AI Chip Owners hub tracks how much computing capacity is held by different entities, broken down by specific chip models, beginning in Q1 2022. These figures include Nvidia and AMD data center GPUs, Google TPUs, Amazon Trainium and Inferentia chips, and Huawei’s AI chips. We estimate that these five categories encompass the vast majority of the world’s dedicated AI computing power. Meta and Microsoft also have their own custom AI chip programs, which are not included here, but they produce far fewer chips than Google’s and Amazon’s. For more details on the methodology used to estimate ownership, see our AI Chip Owners documentation.
Limitations
We convert chip computing capabilities into H100 equivalents (H100e) based on their relative FLOP/s specifications, specifically their maximum 8-bit specification. However, different chips have different strengths and weaknesses (e.g., memory capacities and bandwidths, software stability). Depending on the use case, an H100e provided by an MI300X chip may be more or less effective than an H100e provided by a TPUv6 or B300 chip. Conversions are thus approximate, and are most accurate for model training, which is typically compute rather than bandwidth-bottlenecked.



