Manufacturing Lag

The Chip Sales Hub estimates quarterly chip shipments in part from chip designers’ disclosed revenue. But the quarter in which a chip is sold is not necessarily the quarter in which its semiconductor components were manufactured or consumed. Logic dies, HBM, and advanced packaging capacity are consumed before the finished accelerator is recognized as revenue or shipped to a customer.

To estimate quarterly component consumption, we therefore shift chip volumes backward from the quarter in which they are sold to the quarter or quarters in which their inputs were likely consumed. This is necessarily an approximation: production timelines vary by chip, designer, inventory strategy, supply chain dynamics, and quarter.

For each component, we define “consumption” to match the timing convention used in the corresponding supply denominator.

For logic wafers, we count consumption at wafer completion / shipment, not wafer start. Our logic supply denominator is derived from TSMC’s process-node wafer revenue, and TSMC reports node mix as a share of wafer revenue from shipments. For example, in 4Q25, TSMC noted that “shipments of 3-nanometer accounted for 28% of total wafer revenue.” Since the supply denominator is based on completed wafer shipments, we align demand to the point when the relevant logic wafer is completed and transferred. We assume this occurs roughly 10 weeks before the finished accelerator is shipped or sold. A 10-week lag is shorter than a full calendar quarter, so the associated consumption splits across the prior quarter and the shipment quarter. We use a 10/13–3/13 split: roughly 77% of logic demand is assigned to the prior quarter and 23% to the shipment quarter.

For CoWoS, the denominator is different. Public CoWoS estimates are usually reported as wafers per month of packaging capacity, not revenue from completed packages. We therefore count CoWoS consumption when a chip enters and occupies the packaging flow. This better matches the capacity constraint: a package consumes scarce CoWoS capacity while it is moving through the line, not only when it exits. We assign HBM to the same timing because HBM is committed to the package at the CoWoS stage.

We assume CoWoS and HBM consumption occurs roughly eight weeks before the finished accelerator is shipped or sold. An eight-week lag is shorter than a full calendar quarter, so the associated consumption often falls across both the prior quarter and the shipment quarter. We therefore use a simple 2/3–1/3 split: two-thirds of HBM and CoWoS demand is assigned to the prior quarter, and one-third is assigned to the shipment quarter. Intuitively, this assumes production is spread roughly evenly across the quarter. For a chip shipped during a given quarter, an eight-week lookback will usually place most of the packaging-stage activity in the prior quarter, but a meaningful share remains in the same quarter, especially for chips shipped later in the quarter. This split is an approximation, but it better captures the shorter lag for HBM and CoWoS than assigning all consumption to the prior quarter.

This timing treatment is approximate, but the principle is consistent: logic demand is aligned to completed wafer shipments because the supply denominator is shipment-based, while CoWoS demand is aligned to packaging-line usage because the supply denominator is capacity-based.

Estimating Q4 2025 Consumption

One consequence of the lag between chip sales and manufacturing is that estimating Q4 2025 consumption requires information about Q1 2026 shipment volumes. Many of the chips sold in Q1 2026 would have already consumed semiconductor inputs in Q4 2025, or even earlier, depending on the stage of production.

We therefore need to estimate production that occurred before the end of 2025 but was not captured in Q4 2025 revenue. The available evidence varies by designer and we take a different approach for each. For AMD, Q1 2026 shipment volumes can be estimated from their Q1 26 earnings release, so most Q4 2025 component consumption is captured through the standard lagged-shipment path. For NVIDIA, Q1 2026 shipment volumes are not yet observable, so we use the Jan. 2026 inventory balance to proxy for late-2025 production not yet captured in revenue. For Google and Amazon, balance-sheet inventory is not informative because their chips are manufactured through external partners, so we extrapolate Q1 2026 volumes from 2025 production trajectories.

NVIDIA

For NVIDIA, Q1 2026 shipment volumes are not yet fully observable. To account for this, we use NVIDIA’s year-end 2025 inventory balances as a proxy for production that had occurred but had not yet been recognized as revenue. Work-in-process inventory captures chips and components that are still moving through the production process, while finished-goods inventory captures completed products that have not yet been sold. Both categories can therefore reflect logic wafers, HBM, and advanced packaging capacity consumed before year-end 2025. We use these balances to estimate the portion of Q4 2025 production, and associated component consumption, that is not captured by Q4 2025 sales.

This approach relies on a sell-through assumption: WIP that is close to completion, along with finished-goods inventory on the year-end balance sheet, is assumed to convert into shipments within roughly one quarter. This assumption, while not strictly true, is sensible for NVIDIA. NVIDIA is the market leader in AI accelerators, and demand for its GPUs remains exceptionally high, so year-end inventory is more likely to reflect near-term shipments rather than excess supply. However, NVIDIA can hold GPUs in inventory for several quarters in some cases. For example, Reuters reported that NVIDIA had roughly 700,000 H200s in stock at the end of 2025 that they likely intended to sell to Chinese customers once H200 exports were approved, which we cover further below.

Inventory Timing and Quarterly Attribution

We attribute inventory to the quarter in which the underlying semiconductor inputs were consumed, rather than the quarter in which the inventory appears on the balance sheet. This matters because raw materials, work-in-process inventory, and finished goods represent different stages of production.

For raw materials, we do not apply an additional manufacturing lag. We assume the data center GPU share of raw materials is primarily HBM, alongside substrates and other components. The relevant event is the purchase or receipt of HBM, not the completion of a chip. We therefore phase raw-materials inventory directly across the quarters in which we estimate the HBM was procured. Since HBM3E supply ramped most sharply in the second half of 2025, we attribute the year-end stockpile as 30% in Q3 and 70% in Q4 2025.

For work-in-process, we apply a separate inventory timing treatment rather than the standard shipment lag. WIP is a point-in-time inventory balance: it represents chips or components that NVIDIA already owns or controls, but that have not yet reached finished-goods inventory. We model WIP as a mix of chips that have consumed only logic wafer capacity and chips that have also consumed HBM and packaging capacity.

At the median, we assume 70% of WIP has reached the packaging stage and has therefore consumed logic, HBM, and CoWoS. The reasoning is based on the relative time a chip spends at each stage of WIP. A GPU enters WIP when its logic die is received from TSMC. It then spends roughly 1–4 weeks for wafer testing and dicing and then CoWoS packaging begins, followed by another ~8 weeks moving through CoWoS packaging, final assembly, and testing before reaching finished goods. This means only about less than one-third of WIP time is spent in the logic-only stage, and the remaining more than two-thirds is past CoWoS start. Thus, we assume that, at any given snapshot, roughly 70% of WIP units have already consumed HBM and CoWoS capacity. We model this share as uncertain (range 55%–82%) to capture variation in lead times across chip generations and year-end production effects.

We attribute WIP component consumption mostly to Q4 2025. Chips still in WIP at NVIDIA’s fiscal year-end on Jan. 26, 2026, were likely in active production shortly before the snapshot. Even for WIP chips that had reached CoWoS packaging or final testing, the associated logic wafer fabrication likely occurred roughly 8–12 weeks earlier, placing it mostly in calendar Q4 2025. HBM and CoWoS integration occur later in the process and are therefore also likely to fall in Q4 for chips still in WIP at the Jan. 26 snapshot.

This treatment may overstate Q4 2025 consumption because NVIDIA’s fiscal year-end falls nearly four weeks after calendar year-end. Some inventory captured in the Jan. 26 balance corresponds to component consumption in early calendar Q1 2026. We accept this approximation for simplicity and because the WIP balance is intended to capture NVIDIA’s late-2025 production pipeline rather than precisely date each unfinished unit.

For finished goods, we apply the standard manufacturing lag. Finished goods are completed accelerators, so we can treat their assigned production quarter as a completion event. We back-shift logic die fabrication using the 10-week lag (10/13 prior quarter, 3/13 same quarter) and CoWoS/HBM integration using the standard two-thirds prior-quarter / one-third same-quarter split. NVIDIA’s finished-goods balance is phased across fiscal Q2, Q3, Q4 2025 at 5%, 10%, 85%, respectively. We then map those fiscal-quarter finished-goods balances into calendar-quarter component consumption using the standard manufacturing lags.

The core NVIDIA timing assumptions are:

We apply the following consumption assumptions:

Raw materials: We model HBM as 30%–70% of GPU-attributable raw materials, with a median of 50%.

Work-in-process: We attribute WIP consumption across chip types with meaningful uncertainty. NVIDIA WIP is assumed to consist predominantly of Blackwell-generation chips: B300 at a median of 80%, with a 70%–90% range, and B200 at a median of 20%, with a 10%–30% range. By Q4 2025, the Blackwell ramp had largely displaced Hopper in the production pipeline, and B300 accounted for 63% of unit sales. Since we expect the B300 share of sales to continue rising, we model NVIDIA WIP as 80% B300 at the median.

Finished goods: We use NVIDIA’s full January 2026 finished-goods balance of $8.8B, adjusted for stranded H200 inventory as described below. After deducting stranded H200 inventory, we allocate the remaining finished-goods balance across Blackwell chips, with B300 at a median of 75% and B200 at a median of 25%.

AMD

AMD is treated differently because we can estimate Instinct shipments from its Q1 FY2026 earnings. With the standard manufacturing lag, those Q1 2026 shipments already capture much of AMD’s Q4 2025 logic, HBM, and CoWoS consumption. This means AMD’s Dec. 2025 WIP balance is largely an intermediate pipeline snapshot of chips that later flowed into Q1 2026 shipments. Modeling that WIP separately would risk counting the same production twice.

However, shipment-based volumes may still undercount AMD’s component consumption if AMD manufactured Instinct GPUs that consumed semiconductor inputs but remained unsold after the Q1 FY2026 shipment window. This risk is higher for AMD than for NVIDIA. AMD’s Instinct sales were more uneven, with weaker MI325X demand than expected, MI308X export-control disruption, and even a sequential decline in Data Center AI revenue from Q4 FY2025 to Q1 FY2026. These factors make AMD’s sell-through assumption weaker: completed Instinct GPUs may have accumulated in inventory rather than flowing cleanly into near-term shipments.

AMD’s inventory disclosures support this treatment. AMD said its 2025 inventory increase was primarily to support the continued ramp of Data Center products in advanced process technology nodes. The composition of the inventory build is also informative: from FY2024 year-end to FY2025 year-end, raw materials increased from roughly $350M to $909M (+159%), WIP increased from roughly $4.3B to $4.8B (+11%), and finished goods increased from roughly $1.1B to $2.2B (+105%). This suggests that AMD’s production pipeline remained large, but the incremental inventory build was concentrated in inputs procured ahead of future production and completed products sitting on the balance sheet, rather than a proportional increase in unfinished WIP.

Finished goods are therefore different from WIP. AMD’s Mar. 2026 finished-goods balance represents completed products that still had not shipped after the Q1 FY2026 shipment window. These GPUs consumed logic, HBM, and CoWoS capacity, but are not captured by the Q1 FY2026 shipment path. We therefore exclude AMD WIP, but include a separate finished-goods adjustment for completed Instinct GPUs that remained unsold at the end of Q1 FY2026.

AMD raw materials also remain relevant because HBM procurement is a separate event from packaging-stage HBM attachment. Raw-material HBM may have been purchased before a chip entered packaging, so it is not fully captured by the shipment-based lag adjustment.

AMD’s Mar. 2026 inventory balances are:

Google and Amazon

For Google and Amazon, we take a different approach. Unlike NVIDIA and AMD, which hold finished chip inventory, Google and Amazon rely on external backend partners for chip manufacturing and packaging, so finished chips that haven’t been shipped yet do not appear on their balance sheets. Given that the inventory approach is infeasible for Google and Amazon, we extrapolate Q1 2026 volumes from their 2025 production trajectories.

For Amazon, we project forward from the 2025 Trainium2 trajectory. Volumes grew at roughly 17% quarter-on-quarter through 2025: 210k, 250k, 290k, and 335k units. A log-linear regression, a geometric-mean projection, and a cross-check against AWS’s announced FY2026 capex guidance of $200B all converge on approximately 390,000 units for Q1 2026. For simplicity, we model Amazon’s Q1 2026 ASIC production as Trainium2, though some Trainium3 production is already underway. We apply ±30% uncertainty bands to account for ramp-timing uncertainty and ambiguity around the Trainium2/Trainium3 generation mix.

For Google, we estimate Q1 2026 TPU volumes using Broadcom’s fiscal Q2 2026 AI semiconductor guidance. Broadcom guided to $10.7B of AI semiconductor revenue for fiscal Q2 2026. We first separate AI networking from custom ASIC revenue. On Broadcom’s fiscal Q1 2026 earnings call, management stated that AI networking represented roughly one-third of AI revenue in fiscal Q1 and was expected to rise to about 40% in fiscal Q2. We therefore estimate fiscal Q2 AI networking revenue at $4.28B and the remaining custom ASIC / XPU revenue pool at $6.42B.

We assume Google TPUs account for 85% of Broadcom’s custom ASIC / XPU revenue in fiscal Q2 2026. This implies Google TPU-related revenue of approximately $5.46B for Broadcom in fiscal Q2 2026.

We added this fiscal Q2 2026 TPU revenue row to the input sheet used by our TPU volumes script. The script then converts the fiscal-quarter revenue estimate into calendar-quarter TPU volumes using the same revenue-to-unit conversion logic used for prior TPU quarters. This gives us a calendar Q1 2026 TPU volume estimate that can be fed into the component-consumption model and lagged backward into the quarters in which logic wafers, HBM, and CoWoS packaging capacity were consumed. The resulting Q1 2026 TPU unit estimates are:

Export Control Write-Downs

Changes to export control restrictions resulted in chips that were manufactured but could not be sold. These chips consumed logic wafer, HBM, and advanced packaging capacity during production, but would not appear in revenue if they were blocked from sale by export restrictions. We therefore add the write-down volumes back into demand and attribute consumption to the quarters in which we estimate the chips were manufactured.

NVIDIA disclosed a $1.9B inventory write-down on H20 GPUs following US export restrictions in April 2025. Converting at H20 bill-of-materials cost yields approximately 600,000–700,000 units. This aligns with independently reported estimates of 600,000–700,000 H20 GPUs caught by export controls, providing a point of validation for our BOM model.

We assume the affected H20s were finished and added to inventory primarily in the months immediately before the restrictions took effect. We weight the split toward Q1 2025 because H20 sales volumes remained high in both Q4 2024 and Q1 2025, at roughly 350,000 units per quarter, implying that much of the H20 output from earlier quarters was likely sold rather than held in inventory. The April 2025 write-down, therefore, was likely from a more recent inventory build-up, with most of the affected units produced in Q1 2025 shortly before the new restrictions took effect.

The table below shows the median assumed timing of when the affected H20 units were completed and added to inventory.

While the units were mostly completed in Q1 and Q2 2025, the component inputs for these chips were consumed before the finished GPU entered inventory. We apply our manufacturing lags, which models H20s completed in February, March, and April 2025, consuming logic wafer capacity in roughly December 2024, January 2025, and February 2025, respectively. Their HBM and CoWoS capacity would have been consumed in roughly December 2024, January 2025, and February 2025, respectively.

As a result, even though the affected H20s were finished mostly in Q1 2025 and early Q2 2025, a meaningful share of their semiconductor inputs was consumed in Q4 2024.

AMD recorded a gross $800M write-down on MI308X inventory in Q2 2025, partially reversed by $360M in Q4 2025 when export licenses were granted and those units were sold. The net unresolved provision is $440M. Since the sold chips and the written-down chips came from the same production batch, we treat both tranches identically for timing purposes: converting the full batch at MI308X bill-of-materials cost and applying the same Q4 2024 / Q1 2025 production split used for H20. The Q4 2025 MI308X shipments that appear in the Chip Sales Hub are excluded from the standard shipped-units calculation to avoid double-counting.

H200 Inventory

Reuters reported that NVIDIA had around 700,000 H200 units in inventory at the end of 2025. These chips consumed supply chain capacity during production but had not yet generated revenue by year-end.

We attribute these units to the quarters in which they were produced rather than treating them as Q4 2025 inventory. The table below shows the median assumed timing of when the stranded H200 units were completed and added to inventory.

This spread is based on two assumptions, but holds significant uncertainty. First, NVIDIA is unlikely to hold large volumes of finished GPUs in inventory across many quarters, especially for products that still have strong demand. H200s made up the majority of units sold in Q4 2024, with roughly 680,000 units sold, suggesting that the H200 production line was operating at scale entering 2025. H200 sales also remained meaningful in Q1 2025, at roughly 330,000 units. We therefore assume most of the stranded H200 inventory came from relatively recent production rather than from chips built early in 2025 and held for the rest of the year.

Second, we still taper H200 production by late 2025 because Blackwell was moving into full production and sales. As Blackwell absorbed more of NVIDIA’s HBM, CoWoS, and advanced-node logic capacity, H200 production likely declined. This is why we do not place most stranded H200 production in Q4, even though the inventory was reported at year-end. Instead, we model the largest share in Q3: recent enough to plausibly remain in inventory at year-end, but early enough that H200 lines and supply commitments may still have been meaningfully active before the Blackwell ramp fully displaced Hopper-generation production.

In the finished goods accounting, we value the 700,000 stranded H200 units at H200 bill-of-materials cost ($3,480) and deduct that amount ($2.45B) from NVIDIA’s total finished goods balance before allocating residual dollars to Blackwell chips. This ensures H200 and Blackwell production are attributed to their respective consumption quarters without double-counting.